1. Field of the Invention
The present invention generally relates to a thin film transistor array substrate and a photolithography process and a design of the mask thereof. More particularly, the present invention relates to a thin film transistor array substrate and a photolithography process and a design of the mask thereof for reducing the exposure time and eliminate the trace generated by the junction of the exposure process.
2. Description of the Related Art
In general, a thin film transistor liquid crystal display (TFT-LCD) is constructed by a thin film transistor (TFT) array substrate and a color filter array substrate and a liquid crystal layer. The thin film transistor array substrate is constructed by a plurality of array aligned thin film transistors and a plurality of pixel electrodes, in which each of the thin film transistor is connected to a corresponding pixel electrodes. Each of the thin film transistors includes a gate, a channel layer, a drain and a source. The thin film transistor is generally used as a switch element of a liquid crystal display unit. The working principle of the thin film transistor is similar to that of a conventional metal oxide semiconductor (MOS) element having three terminals (a gate, a drain and a source).
A thin film transistor array substrate is generally manufactured by performing several photolithography and etching process steps. In other words, the thin film transistor array substrate is manufactured by performing the exposure processes for several times to transform the patterns of a mask to the photoresist layer of a substrate. Next, a development process is performed to pattern the photoresist layer. Then, another etching process is carried out to etch the film layer of the substrate using the patterned photoresist layer as an etching mask to form the desired pattern of the component.
In general, the apparatus used for the exposure process includes a substrate stage for holding the substrate, which is capable of performing a two-dimensional movement, and a mask stage for holding the mask having the predetermined pattern and mask stage is capable of providing a two-dimensional movement. When the exposure process is performed, the pattern of the mask is gradually transferred to the photoresist layer of the substrate by the projection optical system during each step of the movement of the mask stage and the corresponding movement of the substrate stage. The conventional exposure process is substantially classified into two types, namely, a one-time projection exposure process, that is, to transfer the whole pattern in the mask to the whole photoresist layer in one projection step. The other is the step-and-repeat projection exposure process (or so-called scanning type exposure process), that is, to transfer the pattern in the mask to a portion of the photoresist layer in one projection step, and repeat the step for several times to expose the whole photoresist layer. In recently years, in order to enlarge the display area of a liquid crystal display, the scanning type the exposure process is more commonly used in the manufacturing process of large-sized liquid crystal display.
In general, a conventional mask used in a scanning type exposure process of a thin film transistor array substrate is illustrated in FIG. 1. As shown in FIG. 1, the mask 100 includes the peripheral pattern area 110 having a left-sided pattern area and a right-sided pattern area and a central pattern area 120. The central pattern area 120 includes a plurality of pixel patterns 122, and a plurality of driving element bonding patterns 124 disposed in a portion of the edge of the central pattern area 120. In addition, the peripheral pattern area 110 includes a plurality of pixel patterns 112 and a plurality of peripheral circuit patterns 114. A portion of the edges of both sides of the peripheral pattern area 110 also includes a driving element bonding pattern 116. Thereafter, the patterns of the mask 100 are transferred to the photoresist layer of the substrate by moving the mask 100 and the substrate synchronously and performing one or a plurality of exposure processes to the areas. Then, these patterns are jointed with each other. Finally, the exposure process of the mask of the thin film transistor array substrate is completed.
FIG. 2 is a schematic drawing illustrating a conventional thin film transistor array substrate. As shown in FIG. 2, after the exposure process via the patterns of the left and right sides of the peripheral pattern area 110 of the mask 100, the patterns of the peripheral pattern area 110 are transferred to the photoresist layer (not shown) of the substrate 150. After a development process, an etching process is performed to etch the film layer using the patterned photoresist layer as an etching mask, and thus the peripheral element area 110a of the left and right sides of the substrate 150 is formed. Each of the left and right sided of the peripheral element area 110a includes a pixel structure 112a, a peripheral circuit 114a and a driving element bonding area 116a respectively. In addition, after performing a plurality of exposure processes to the central pattern area 120 of the mask 100, the pattern of the central pattern area 120 of the mask 100 is transferred to the photoresist layer of the substrate 150. Then, after performing a development process and an etching process using the patterned photoresist layer as an etching mask, central pattern areas 120a, 120b and 120c of the substrate 150 are formed in the film layer on the substrate 150. Wherein the central pattern areas 120a, 120b and 120c include pixel structures 122a and driving element bonding areas 124a respectively.
Referring to FIG. 1 and FIG. 2, the pixel structures 122a of the central pattern areas 120a, 120b and 120c, and the pixel structures 112a of the peripheral element area 110a are connected along the junction lines L1 to L4. Finally, a panel-display area 130 (the area surrounded by the dotted line in FIG. 2) is formed. Since the junction lines L1 to L4 is located in the panel-display area 130, a trace along the junction lines L1 to L4 may be generated due to the alignment errors of the mask 100 during the exposure processes.
Accordingly, in the above-described scanning type exposure process, the advantages are as following: an excellent imaging property can be maintained, and a large-scale exposure area can be achieved without using a large-sized expose device such as a mask and a stage. However, in the above-described scanning type exposure process, some junction lines in the panel-display area are formed during the exposure processes by using the central pattern area, and the other junction lines in the panel-display area are formed during the transferring of the left and right sided pattern areas of the peripheral element area and that of the central pattern areas. If some alignment errors occur during the alignment of the mask in the exposure process, some traces may be generated along the junction lines in the panel-display area, then the uniformity of the brightness of the whole panel may be reduced.